Division B-4 · VLSI

Physical Design
to Silicon Sign-Off

Place-and-route, clock tree synthesis, timing closure, and GDSII delivery — every step targeted at first-pass tapeout readiness.

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Physical Design at Quantova
Overview

From Netlist to Tapeout-Ready GDSII

What is Physical Design? After a chip's logic is written and verified, it must be physically laid out — every transistor, wire, and circuit element placed and routed on the silicon die. Physical design is this layout work. The final output (GDSII) is the manufacturing file sent directly to the chip factory.

Quantova physical design engineers take your synthesis netlist through complete physical implementation — floorplanning, power planning, place-and-route, CTS, ECO, and STA sign-off — delivering a clean GDSII with all sign-off reports.

What We Deliver

Core Capabilities

Floorplanning & Power

Die size estimation, block placement, power rail planning, and IR drop analysis targeting your area and power budget.

Place & Route

Standard cell placement and routing with congestion-driven strategies to meet timing, density, and DRC targets.

CTS & Timing Closure

Clock tree synthesis targeting skew and insertion delay specs, followed by hold/setup STA closure across all corners.

Sign-Off Checks

LVS, DRC, ERC, and antenna checks using Calibre or equivalent. GDSII delivered clean with sign-off reports.

Deliverables

What You Receive

  • Tapeout-ready GDSII (manufacturing file sent directly to the chip factory)
  • STA sign-off reports (all PVT corners)
  • LVS/DRC/ERC clean reports
  • Power analysis and IR drop report
  • Floorplan and block-level documentation
PDK required: Physical design requires your foundry PDK. We work under NDA and return all PDK data on project completion.
Technology Stack

Tools & Platforms

Cadence Innovus Synopsys ICC2 Synopsys PrimeTime Siemens Calibre Mentor Hyperlynx OpenROAD
FAQs

Common Questions

We have taped out or completed physical design at TSMC 28nm/16nm, GF 22nm, UMC 40nm, and several 130nm–180nm nodes. We work within any PDK you provide.

Yes. We can audit the current state, identify timing or DRC issues, and continue from that point — no need to restart from netlist.

Begin Physical Implementation

Provide your synthesis netlist, timing constraints, and PDK information. We will review and scope the physical design effort.

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